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[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[Embeded-SCM Develop] NIOS_II_IP

Description: 基于双NIOS II 的IP无线收发机 2006年嵌入式电子大赛获奖作品-NIOS II-based IP wireless transceiver embedded electronic 2006 Championship winning entries
Platform: | Size: 381952 | Author: 刘斐 | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: crc校验，非常好用，是从Xilinx的IP演化来的-crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟
Platform: | Size: 10240 | Author: zl | Hits:

[VHDL-FPGA-Verilog] 2C35F672_FFT

Description: 在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
Platform: | Size: 474112 | Author: lovenevol | Hits:

[VHDL-FPGA-Verilog] NCO_ip

Description: NCO的VHDL程序，是利用IP核生成的，超好的，快下吧-NCO of the VHDL process is the use of nuclear-generated IP, super good, fast, are you
Platform: | Size: 128000 | Author: 张俊 | Hits:

[Software Engineering] Wishbone_from_opencores

Description: 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。-This is collected in OPENCORE Wishbone bus and guide the development of note, with the electronic design of a large number of open source IP applications, wishbone bus is also becoming increasingly popular.
Platform: | Size: 836608 | Author: 刘庆强 | Hits:

[VHDL-FPGA-Verilog] VGA_LCD_IP

Description: vga ipcore的verilog代码
Platform: | Size: 495616 | Author: | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[VHDL-FPGA-Verilog] 15AlteraDEIP

Description: 15个Altera的IP的源码.15个Altera的IP的源码-15 Altera s IP source .15 months of Altera s IP source
Platform: | Size: 49152 | Author: 11 | Hits:

[SCM] 8051ipcore

Description: 8051的IP内核，用verilog编写，可以实现8051的一般功能-8051 IP core, prepared using Verilog, you can realize the general function of 8051
Platform: | Size: 52224 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] 8255

Description: Verilog语言描述的Intel8255 IP Core，本人已经在某项目中经过了物理验证的，可直接用于FPGA综合或ASIC综合。
Platform: | Size: 6144 | Author: David.Mr.Liu | Hits:

[Embeded-SCM Develop] niosii_vga_ref_des

Description: VGA核的verilog实现，能用于NIOS2的avalon总线-VGA core Verilog realize, can be used to NIOS2 the avalon bus
Platform: | Size: 617472 | Author: 李永杰 | Hits:

[Post-TeleCom sofeware systems] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。-Altera
Platform: | Size: 1355776 | Author: YangJun | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] camera.tar

Description: 摄像头的硬件函数，ip核，用于xilinx公司的virtex4 fpga-Camera
Platform: | Size: 416768 | Author: 惠普 | Hits:

[VHDL-FPGA-Verilog] bluetooth

Description: ip核，蓝牙bluetooth的fpga硬件实现-ip nuclear, Bluetooth bluetooth realize the FPGA hardware
Platform: | Size: 16384 | Author: 惠普 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA
Platform: | Size: 23552 | Author: 王鹏 | Hits:

[MPI] I2C

Description: I2C总线的verilog 程序，非常有用，已经经过验证。-Verilog I2C bus procedures, very useful, has been verified.
Platform: | Size: 70656 | Author: LLT | Hits:
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